The prior art is replete with different techniques and processes for fabricating semiconductor devices such as metal oxide semiconductor (MOS) transistors. In accordance with typical fabrication techniques, a MOS transistor is formed by creating a device structure on a semiconductor substrate, where the device structure includes a gate stack formed on a layer of semiconductor material, and source and drain regions formed in the semiconductor material to define a channel region under the gate stack. In addition, embedded strain elements (i.e., doped/undoped semiconductor material that strains the channel region) can be used to improve the performance of MOS transistors. In this regard, FIG. 1 is a cross sectional view of a MOS transistor device structure 100 having such embedded strain elements 102 located within a layer of semiconductor material 104. FIG. 1 depicts MOS transistor device structure 100 at an intermediate stage in the overall fabrication process.
In practice, the minimum distance between doped embedded strain elements in the semiconductor material (near the channel region) is limited due to the out-diffusion of the doped species into the channel region. Such out-diffusion exacerbates the short channel effect (SCE) that occurs in MOS transistors fabricated using modern small scale process nodes, for example, 45 nm nodes and beyond. To better control SCE, MOS transistor device structure 100 employs embedded strain elements 102 having a stepped profile, as shown in FIG. 1. The stepped profile results in a relatively narrow separation between the upper portions 106 of embedded strain elements 102, and a relatively wide separation between the lower portions 108 of embedded strain elements 102. This structure facilitates the realization of shallow junctions for better SCE control.
The conventional technique for fabrication of stepped embedded strain elements requires multiple photolithography, etching, and spacer formation steps. Referring to FIG. 1, dual-recess cavities 110 in semiconductor material 104 are formed in the following manner. After formation of a gate stack 112, sidewall spacers 114, and offset spacers 116, an appropriate etch mask is formed. Then, first recesses are etched into semiconductor material 104; these first recesses will be aligned with offset spacers 116. The first recesses represent the relatively deep pockets of dual-recess cavities 110. After formation of the first recesses, offset spacers 116 are removed (as indicated by the dashed lines in FIG. 1) and an appropriate etch mask is formed. Then, second recesses are etched into semiconductor material 104. These second recesses will be aligned with sidewall spacers 114. The second recesses represent the relatively shallow extensions of dual-recess cavities 110. This process, which employs multiple masking and etching steps, can be expensive, time consuming, and difficult to control.